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1 features ? serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) ? data sheet describes mode 0 operation medium-voltage and standard-voltage operation ? 5.0 (v cc = 4.5v to 5.5v) ? 2.7 (v cc = 2.7v to 5.5v) extended temperature range ? 40c to +125c 5 mhz clock rate 64-byte page mode and byte write operation block write protection ? protect 1/4, 1/2, or entire array write protect (wp ) pin and write disable instructions for both hardware and software data protection self-timed write cycle (5 ms max) high reliability ? endurance: 100,000 write cycles ? data retention: >100 years 8-lead pdip, 8-lead jedec soic, and 8-lead tssop packages description the at25128a/256a provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read-only memory (eeprom) organized as 16,384/32,768 words of 8 bits each. the device is optimized for use in many industrial and automotive applications where low-power and low-voltage operation are essential. the devices are available in space-saving 8-lead pdip, 8-lead jedec soic, and 8-lead tssop packages. the at25128a/256a is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no sepa- rate erase cycle is required before write. table 1. pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input nc no connect dc don't connect 5088c?seepr?11/04 spi serial extended temperature eeproms 128k (16,384 x 8) 256k (32,768 x 8) at25128a at25256a 1 2 3 4 8 7 6 5 8 -le a d pdip 1 2 3 4 8 7 6 5 8 -le a d s oic 1 2 3 4 8 7 6 5 8 -le a d t ss op c s s o wp gnd vcc hold s ck s i c s s o wp gnd vcc hold s ck s i c s s o wp gnd vcc hold s ck s i
2 at25128a/256a 5088c?seepr?11/04 block write protection is enabled by programming the status register with top one-forth, top one-half, or entire array of write protection. separate program enable and program disable instructions are provided for additi onal data protection. hardware data protec- tion is provided via the wp pin to protect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence . figure 1. block diagram absolute maximum ratings* operating temperature ......................................? 40 c to +125 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma 16384/32768 x 8
3 at25128a/256a 5088c?seepr?11/04 note: 1. this parameter is characterized and is not 100% tested. note: 1. maximum value at +125c 2. v il and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6pfv in = 0v table 3. dc characteristics applicable over recommended operating range from t ae = ? 40c to +125c, v cc = +2.7v to +5.5v symbol parameter test condition min typ max units v cc1 supply voltage 2.7 5.5 v v cc2 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v at 1 mhz, so = open, read 2.0 3.0 ma i cc2 supply current v cc = 5.0v at 2 mhz, so = open, read, write 3.0 5.0 ma i cc3 supply current v cc = 5.0v at 5 mhz, so = open, read, write 3.5 6.0 ma i sb1 standby current v cc = 2.7v, cs = v cc 0.5 12.0 (1) a i sb2 standby current v cc = 5.0v, cs = v cc 2.0 15.0 (1) a i il input leakage v in = 0v to v cc ? 3.0 3.0 a i ol output leakage v in = 0v to v cc ? 3.0 3.0 a v il (2) input low-voltage ? 1.0 v cc x 0.3 v v ih (2) input high-voltage v cc x 0.7 v cc + 0.5 v v ol1 output low-voltage 3.6 v cc 5.5v i ol = 3.0 ma 0.4 v v ol2 output low-voltage 2.7 v cc 3.6v i ol = 0.15ma 0.2 v v oh1 output high-voltage 3.6 v cc 5.5v i oh = ? 1.6 ma v cc ? 0.8 v v oh2 output high-voltage 2.7 v cc 3.6v i oh = ? 100 ma v cc ? 0.2 v
4 at25128a/256a 5088c?seepr?11/04 note: 1. this parameter is characterized and is not 100% tested. contact atmel for further information. table 4. ac characteristics applicable over recommended operating range from t ae = ? 40 c to +125 c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter voltage min max units f sck sck clock frequency 2.7?5.5 0 5.0 mhz t ri input rise time 2.7?5.5 2 s t fi input fall time 2.7?5.5 2 s t wh sck high time 2.7?5.5 40 ns t wl sck low time 2.7?5.5 40 ns t cs cs high time 2.7?5.5 80 ns t css cs setup time 2.7?5.5 80 ns t csh cs hold time 2.7?5.5 80 ns t su data in setup time 2.7?5.5 5 ns t h data in hold time 2.7?5.5 20 ns t hd hold setup time 2.7?5.5 40 ns t cd hold hold time 2.7?5.5 40 ns t v output valid 2.7?5.5 0 40 ns t ho output hold time 2.7?5.5 0 ns t lz hold to output low z 2.7?5.5 0 40 ns t hz hold to output high z 2.7?5.5 80 ns t dis output disable time 2.7?5.5 80 ns t wc write cycle time 2.7?5.5 5 ms endurance (1) 5.0v, 25 c, page mode 100k write cycles
5 at25128a/256a 5088c?seepr?11/04 serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25128a/256a always operates as a slave. transmitter/receiver: the at25128a/256a has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25128a/256a, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the at25128a/256a is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the so pin will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25128a/256a. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communi cation with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin (wp ) will allow normal read/write operations when held high. when the wp pin is brought low and wpen bit is ?1?, all write opera- tions to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write op eration to the status register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow the user to install the at25128a/256a in a system with the wp pin tied to ground and still be able to write to the status register. all wp pin functions are enabled when the wpen bit is set to ?1?.
6 at25128a/256a 5088c?seepr?11/04 figure 2. spi serial interface at25128a/256a
7 at25128a/256a 5088c?seepr?11/04 functional description the at25128a/256a is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the at25128a/256a utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 5. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. write enable (wren): the device will power-up in the write disable state when v cc is applied. all programming instructions must therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is indepen- dent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction . write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection. the at25128a/256a is divided into four array segments. table 5. instruction set for the at25128a/256a instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array table 6. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy table 7. read status register bit definition bit definition bit 0 (rdy ) bit 0 = ?0? (rdy ) indicates the device is ready. bit 0 = ?1? indicates the write cycle is in progress. bit 1 (wen) bit 1 = ?0? indicates the device is not write enabled. bit 1 = ?1? indicates the device is write enabled. bit 2 (bp0) see table 8. bit 3 (bp1) see table 8. bits 4?6 are ?0?s when device is not in an internal write cycle. bit 7 (wpen) see table 9. bits 0?7 are ?1?s during an internal write cycle.
8 at25128a/256a 5088c?seepr?11/04 top quarter, top half, or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protection levels and corresponding status register control bits are shown in table 8. bits bp0, bp1, and wpen are nonvolatile cells that have the same properties and func- tions as the regular memory cells (e.g., wren, t wc , rdsr). the wrsr instruction also allows the user to enable or disable the write protect (wp ) pin through the use of the write protect enable (wpen) bit. hardware write protection is enabled when the wp pin is low and the wpen bit is ?1?. hardware write protection is disabled when either the wp pin is high or the wpen bit is ?0?. when the device is hard- ware write protected, writes to the status register, including the block protect bits and the wpen bit, and the block-protected sections in the memory array are disabled. writes are only allowed to sections of the memory that are not block-protected. note: when the wpen bit is hardware write protected, it cannot be changed back to ?0? as long as the wp pin is held low. read sequence (read): reading the at25128a/256a via the so pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (see table 10). upon completion, any data on the si line will be ignored. the data (d7?d0) at the spec- ified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be contin- ued since the byte address is automatically incremented and data will continue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address, allowing the entire memory to be read in one continuous read cycle. write sequence (write): in order to program the at25128a/256a, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field loca- table 8. block write protect bits level status register bits array addresses protected bp1 bp0 at25128a at25256a 0 0 0 none none 1 (1/4) 0 1 3000?3fff 6000?7fff 2 (1/2) 1 0 2000?3fff 4000?7fff 3 (all) 1 1 0000?3fff 0000?7fff table 9. wpen operation wpen wp wen protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writeable writeable 1 low 0 protected protected protected 1 low 1 protected writeable protected x high 0 protected protected protected x high 1 protected writeable writeable
9 at25128a/256a 5088c?seepr?11/04 tion selected by the block write protection level. during an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transmitted via the si line followed by the byte address and the data (d7?d0) to be programmed (see table 10). programming will start after the cs pin is brought high. the low-to-high transition of the cs pin must occur dur- ing the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read status register (rdsr) instruction. if bit 0 = ?1?, the write cycle is still in progress. if bit 0 = ?0?, the write cycle has ended. only the rdsr instruction is enabled during the write pro- gramming cycle. the at25128a/256a is capable of a 64-byte page write operation. after each byte of data is received, the six low-order address bits are internally incremented by one; the high order bits of the address will remain constant. if more than 64 bytes of data are transmitted, the address counter will roll ov er and the previously written data will be overwritten. the at25128a/256a is automatically returned to the write disable state at the completion of a write cycle. note: if the device is not write enabled (w ren), the device will ignore the write instruction and will return to the standby state when cs is brought high. a new cs falling edge is required to reinitiate the serial communication. table 10. address key address at25128a at25256a a n a 13 ? a 0 a 14 ? a 0 don?t care bits a 15 ? a 14 a 15
10 at25128a/256a 5088c?seepr?11/04 timing diagrams (for spi mode 0 [0, 0]) figure 3. synchronous data timing figure 4. wren timing figure 5. wrdi timing s o v oh v ol hi-z hi-z t v valid in s i v ih v il t h t s u t di s s ck v ih v il t wh t c s h c s v ih v il t c ss t c s t wl t ho
11 at25128a/256a 5088c?seepr?11/04 figure 6. rdsr timing figure 7. wrsr timing cs sck 01234567891011121314 si instruction so 76543210 data out msb high impedance 15
12 at25128a/256a 5088c?seepr?11/04 figure 8. read timing figure 9. write timing figure 10. hold timing s o s ck hold t cd t hd t hz t lz t cd t hd c s
13 at25128a/256a 5088c?seepr?11/04 at25128a ordering information ordering code package operation range at25128a-10pe-2.7 at25128an-10se-2.7 8p3 8s1 extended temperature ( ? 40 c to 125 c) at25128a-10pq-2.7 at25128an-10sq-2.7 at25128a-10tq-2.7 8p3 8s1 8a2 lead-free/halogen-free extended temperature ( ? 40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) options ? 2.7 low-voltage (2.7v to 5.5v)
14 at25128a/256a 5088c?seepr?11/04 at25256a ordering information ordering code package operation range at25256a-10pe-2.7 at25256an-10se-2.7 8p3 8s1 extended temperature ( ? 40 c to 125 c) at25256a-10pq-2.7 at25256an-10sq-2.7 at25256a-10tq-2.7 8p3 8s1 8a2 lead-free/halogen-free extended temperature ( ? 40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) options ? 2.7 low-voltage (2.7v to 5.5v)
15 at25128a/256a 5088c?seepr?11/04 packaging information 8p3 ? pdip 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 p 3 , 8 -le a d, 0. 3 00" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8 p 3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge g s - 3 . 3 . d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.195 b 0.014 0.01 8 0.022 5 b 2 0.045 0.060 0.070 6 b3 0.0 3 0 0.0 3 9 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view
16 at25128a/256a 5088c?seepr?11/04 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
17 at25128a/256a 5088c?seepr?11/04 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
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